Note: This is the baud rate that the UART is programmed to onĭownload the bitstream by selecting Xilinx → Program FPGA, then Utility with the baud rate set to 115200. If the serial terminal is not open, connect the serial communication This is used for USB to serial transfer.Ĭhange Ethernet Jumper J30 and J43 as shown in the following figure. Mode is controlled by switch SW10 on the ZC702 and SW4 on the ZC706.Ĭonnect a USB cable to connector J17 on the target board with the Mode has to be selected, according to the user interface. Target board JTAG port with the following SW10 switch settings, as shown in Network or directly to your host machine.Ĭonnect the Windows host machine to your network.Ĭonnect a micro USB cable between the Windows host machine and the Itįinishes booting Linux on the target platform.Ĭheck the following board connections and settings for Linux bootingĮnsure that the settings of Jumpers J27 and J28 are set as described in Example 2: Setting Up the Board.Įnsure that the SW16 switch is set to 00000, as shown in the following figure.Ĭonnect an Ethernet cable from the Zynq-7000 SoC board to your Root file system, and the device tree from non-volatile RAM to DDR. The U-Boot loads and starts the execution of the kernel image, the Loads and executes the Linux U-Boot image from non-volatile memory to DDR The FSBL does the following:Ĭonfigures the FPGA with the hardware bitstream (if it exists) On-chip ROM code is responsible for loading the first stage boot The processing system (PS) and it executes on-chip ROM code. The boot process is initiated by one of the Arm® Cortex™-A9 CPUs in Refer to the Zynq-7000 SoC Technical Reference Manual In this method, the master boot method is further divided into secure and non-secure Such as QSPI, NAND, NOR flash, and SD cards are used to store boot Images from non-volatile memory into the processor system (PS). In the master boot method, the CPU loads and executes the external boot
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